Some integrated circuits include both core transistors and input-output (IO) transistors. Core transistors are smaller, occupy less die space, and use lower voltage level signals and a lower supply voltage value. Core transistors operate in a core supply voltage domain. In contrast, IO transistors are larger, occupy a larger die space, and use higher voltage level signals and a higher supply voltage value. IO transistors operate in an IO supply voltage domain. Gate oxides of core transistors are generally thin compared with those of IO transistors. Consequently, core transistors are also called thin oxide or thin transistors while IO transistors are called thick oxide or thick transistors.
For illustration, a condition in which a P-type metal oxide semiconductor (PMOS) transistor and an N-type metal oxide semiconductor (NMOS) transistor have fast responses compared with normal transistors is called a FF condition or a FF corner. In contrast, a condition in which a PMOS transistor and an NMOS transistor have slow responses compared with normal transistors is called an SS condition or an SS corner.
In circuit applications such as in the universal serial bus 3.0 (USB 3.0), peripheral component interconnect express (PCIE) third generation, and the Thunderbolt, serializer/deserializer (SERDES) circuits often use an equalizer and a current mode logic (CML) buffer to amplify received signals. In some existing approaches, a core voltage supply value is used to obtain speed and bandwidth requirements. The CML circuit comprises a resistor and a tail current. The output swing of the amplified signal is based on the tail current and a resistance of the resistor. As a result, the output swing is affected by variations of the tail current and of the resistor with reference to temperature under which the circuits operate.
In some approaches, a precision current mirror circuit having two metal oxide semiconductor (MOS) transistors provides high output impedance, and reduces channel modulation effect of the MOS transistors to minimize the current mirror mismatch. In short channel processes, however, the supply voltage is under 1 V. To get high accuracy for the current mirror, four MOS transistors and one resistor are used in one branch of the differential pair, which results in a low headroom limitation because of the low supply voltage under 1.0 V. In some other approaches, three MOS transistors are used in one branch, which, however, results in a large current mismatch.
In at least two approaches that require a precision current, a large current mismatch results from current mirrors in the circuit. Other deficiencies also exist. For example, in one approach, the voltage swing of an output signal is small in the FF corner. A resistance variation of the SS corner is as high as two times a resistance variation of the FF corner. To obtain a larger output swing at the FF corner, a size of the resistor is increased. In such a condition, however, the resistance of the resistor limits the bandwidth at the SS corner. Further, to keep a transistor operating in the saturation region, the tail current requires a large voltage drop between the drain and the source of the transistor.
Like reference symbols in the various drawings indicate like elements.